As present-day integrated circuits become more dense and more complex, conventional techniques for testing such circuits, which rely on sophisticated prior art testing machines for this purpose, are becoming increasingly less effective. For that reason, much attention is now being devoted to developing techniques for enabling an integrated circuit to test itself (built-in self-test). An example of a built-in self-test technique for a Random Access Memory (RAM) is disclosed in U.S. Pat. No. 4,872,168, issued on Oct. 3, 1989, in the names Duane R. Aadsen et al., and assigned to AT&T Bell Laboratories, the same assignee of the instant application. The Aadsen et al. test technique utilizes a test address generator for successively addressing individual cells within the RAM so that each cell can be written into, and read from, to verify its operation.
The test address generator presently employed to address successive cells in a RAM for self-testing typically employs a fully decoded counter. This type of counter operates by counting up to, or down from, a fixed binary value 2.sup.k -1, where k is an integer. The disadvantage associated with this type of counter is that if the number of cells to be addressed is less than 2.sup.k -1, the counter must still count up to, or down from, 2.sup.k -1 even after all cells have been addressed. Thus, it becomes necessary to wait for the counter to complete counting before a subsequent testing operation can be accomplished. Depending on the difference between the counter count of 2.sup.k -1 and the actual number of cells, the delay can be significant.
Thus, there is a need for a test address generator which can count up to and down from a user-selected value to increase test efficiency.